PSeuDoFFIL: Power Saving Datapath FiFo Insertion Logic
نویسندگان
چکیده
A technique is described to dynamically limit power dissipation in heavily pipelined digital circuits. Stages in the pipeline are clock gated based upon validity of data at that stage. As the pipe approaches a stalled or inactive state, branches of the clock tree are progressively disabled stage by stage. The technique has the additional advantage of removing gaps or “bubbles” in the data streams, improving the latency of the system.
منابع مشابه
Logic Depth and Power Consumption: A Comparative Study Between Standard Cells and FPGAs
In large combinational datapaths, glitches generated in the first stages produce an avalanche effect in the activity of subsequent nodes. This problem can be avoided by registering every few gates. Thus, the propagation of glitches is blocked, and consequently, the datapath power is reduced. However, these extra registers increase the synchronization power. Therefore, for a given technology, th...
متن کاملAn FPGA Based on Synchronous/Asynchronous Hybrid Architecture with Area-Efficient FIFO Interfaces
This paper presents an FPGA architecture that combines synchronous and asynchronous architectures. Datapath components such as logic blocks and switch blocks are designed so as to run in asynchronous and synchronous modes. Moreover, a logic block is presented that implements area-efficient First-in-first-out(FIOF) interfaces, which are usually used for communication between synchronous and asyn...
متن کاملHigh-Performance Two-Phase Micropipeline Building Blocks: Double Edge-Triggered Latches and Burst-Mode Select and Toggle Circuits
This paper presents new high-performance building blocks for two-phase micropipelines. We develop pseudo-static Svensson-style double edge-triggered Dip -ops (DETDFF) for datapath storage in place of traditional capture-pass or transmission gate latches. We compare a DETDFF FIFO buuer implementation with the current state-of-the-art micropipeline implementation using four-phase controllers desi...
متن کاملPower Optimized ALU for Efficient Datapath
With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for microprocessor systems design. Also clock power can be significant in high performance systems. In this paper, a low power ALU for efficient datapath is proposed. In ALU, based on the observation, that while one functional unit is working other functional uni...
متن کاملFSMD Functional Partitioning for Low Power Using Energy Estimation and Bounds
Partitioning a system has been shown an effective method for power reduction. Partitioning can be applied to either the controller or the datapath. A recent FSMD functional partitioning technique have shown that when partitioning is applied to both the controller AND the datapath, a much greater power saving is achievable. However, the partitioning problem is known to be NPcomplete. In this pap...
متن کامل